Computer Organization and Design RISC-V Edition
David Patterson, John Hennessy 저
Elsevier · 2017년 4월 13일 출시
:bulb: 목표
- 컴퓨터 구조를 공부한다.
RISC-V 컴퓨터 하드웨어, 소프트웨어 인터페이스를 자세히 공부한다.
🚩 정리한 문서 목록
📔 Computer Abstractions
response time(execution time): wall clock time(elapsed time), CPU time, clock rate, clock period, CPI(Clock cycles Per Instruction), Effective CPI, MIPS
Power Wall, multicore processor, parallel programming, Amdahl's Law
⚙️ RISC-V
CISC vs RISC, general purpose register(register file), register operands, data alignment(MIPS vs RISC-V), byte addressing, little/big Endian, register spilling, bit extension
R-format instructions(arithmetic), I-format instructions(load, immediate arithmetic), S-format instructions(stores)
addressing mode(immediate, register, base, PC-relative), logical operations(shift, and, or, xor)
branch instructions(if-else, while example), procedure calling, procedure call instructions, memory layout, stack, leaf procedure, non-leaf procedure(factorial example), string copy example
wide immediate operands, branch addressing, SB-format, branching far away
data race, synchronization, atomic swap, mutex lock
🎛 RISC-V Processor
instruction execution: IF(Instruction Fetch), ID(Instruction Decode/register file read), EX(Execute/address calculation), MEM(Memory access), WB(Write Back)
combinational element, state element, sequential elements, multiplexer, control unit(function unit, control line)
single-cycle vs pipelined performance, pipeline bubble, steady state
pipeline hazard: structural hazard, data hazard(forwarding, code scheduling), control hazard(static/dynamic branch prediction)
pipeline register, forwarding, double data hazard
Instruction Level Parallelism, Multiple Issue, Speculation, VLIW(Very Long Instruction Word), Loop Unrolling
🪜 Cache
SRAM, DRAM, temporary locality, spatial locality
hit ratio, miss ratio, direct mapped cache(tag, valid bit, address subdivision), block size considerations
cache miss(compulsory/capacity/conflict misses), cache write(write-through, write buffer, write-back, write allocation)
N-way set-associative cache(miss rate and associativity), fully-associative cache, replacement policy(LRU, random)
split cache(instruction cache, data cache), cache performance(memory-stall clock cycles, AMAT), multilevel caches(primary cache, secondary cache)
⛓ Parallel Processors
interconnection, I/O register mapping(memory mapped I/O, I/O mapped I/O), polling, interrupt
heterogeneous computing, parallel programming, process vs thread, Thread-Level Parallelism(TLP): Temporal Multi-Threading(Coarse-grained, Fine-grained), Simultaneous Multi-Threading(SMT)
Shared Memory Multiprocessor(SMP), Uniform Memory Access, Non-Uniform Memory Access, PThread Programming
Message Passing Interface(MPI), MPI programming